1 Introduction
The LED display is a new type of flat panel display device that appeared in the 1990s. It is popular because of its high brightness, clear picture and bright colors. The full-color LED display utilizes the principle of three primary colors to produce a color effect by superimposing three kinds of LEDs of red, green and blue; the true color LED display has 8-bit gray value for each single primary color, that is, the single pixel is composed of 24-bit RGB binary. The number indicates. The image source of the LED control system is generally a real-time digital signal. To achieve smooth video display, the image with high refresh rate should be transmitted in real time according to the pixel signal corresponding to the LED dot matrix. When the display resolution is large, the transmission is performed. The demand for system bandwidth is huge. Ethernet is a common network standard in life. Applying existing Ethernet technology to LED screen transmission system not only simplifies system design, reduces design cycle, but also facilitates the formation of transmission standards for LED screen control systems. The current Gigabit Ethernet LED control system is limited to the use of a single transmission medium, and cannot combine the advantages of long-distance transmission of optical fibers and low-cost twisted pair networking. In order to solve such problems, this paper analyzes the similarities and differences between Gigabit Ethernet transmissions using two transmission media by studying the related protocols of Gigabit Ethernet [1], and introduces the transmission of 1000BASE-T and 1000BASE-LX physical layer signals in detail. In this way, a media converter based on two standards was designed and applied to an LED transmission system. For the design of the FPGA main controller, the on-chip buffering method of the transmission frame structure and image data is mainly analyzed. The system saves the cost of the LED long-distance real-time transmission system under the premise of ensuring the transmission rate. 
2 Design principles
2.1 Gigabit Ethernet
Gigabit Ethernet technology currently has two standards: IEEE802.3z[2] and IEEE802.3ab. IEEE 802.3z sets standards for fiber and short-range copper connection options, including: 1000BASE-LX, 1000BASE-SX, and 1000BASE-CX. IEEE 802.3ab sets the standard for long-distance connection schemes on five types of twisted pair: 1000BASE-T. This paper selects 1000BASE-LX and 1000BASE-T as the representatives of optical transmission and twisted pair transmission respectively, discusses the application of 802.3z and 802.3ab in LED transmission system and the conversion process between them.
2.2 LED transmission system
The structure of the Gigabit Ethernet LED transmission system [3-5] for twisted pair transmission is shown in Figure 1. The digital video interface obtains the display video source from the PC host; the data cache portion is used to achieve the rate matching between the video source and the network transmission; The Gigabit Ethernet MAC layer at the transmitting end encapsulates the data and constructs a top-level transmission control protocol; the Gigabit network physical layer completes the channel codec of the data, generates the transmission clock, and controls the transmission of the symbol on the physical channel; The layer realizes the extraction of the transmission clock and the channel decoding; the MAC layer performs frame unpacking and checks the data; the data is divided into small area pixel blocks according to the requirements of the scanning system [5-6] according to the area allocation part, and is sent Into the scanning system; the scanning system is responsible for the area display of the LED driver chip control [7-8].
The structure of the Gigabit Ethernet LED transmission system using optical fiber transmission is similar to that of Figure 1, and the specific implementation methods are different. The two transmission media have great advantages in network construction cost and long-distance transmission respectively. The flexible selection of transmission mode can improve the cost performance. In order to combine the advantages of the two transmission modes, it is necessary to design an LED transmission system media converter.
3 Design Ideas 3.1 System Composition
The structure of the Gigabit network media converter is shown in Figure 2. Image source data enters the system through two RJ45 interfaces, each with a rate of 1 Gbit/s. The network transformer converts the signal on the twisted pair into a format that the symbol can recognize. The physical layer is divided into three sub-layers [9], which are a physical coding sublayer (PCS), a physical medium connection sublayer (PMA), and a physical medium dependent sublayer (PMD). The functions implemented by the 1000BASE-T physical layer control chip include the A/D conversion function of the PMD sublayer; the transmission clock recovery function of the PMA sublayer; and the Viterbi decoding and descrambling functions of the PCS sublayer. Two 125M clock 8bit data signals are recovered before the data frame enters the master FPGA. The master FPGA completes the function of the MAC layer, and the two channels of data are separately unpacked and buffered, and the data is divided into 16 bits to form a new frame and added to the control information, and then transferred to the universal Gigabit transceiver; The data is first encoded by the 8B/10B of the fiber PCS sublayer, then sent to the PMA sublayer for parallel and serial conversion, and after the corresponding differential level conversion, enters the PMA sublayer, ie, the SFP optical module, to achieve electro-optical conversion, and finally It is transmitted as an optical signal to a single mode fiber. The data flow direction of the receiving end is completely reversed, and the data enters from the fiber end. In the main control FPGA, the 16-bit frame is re-encapsulated and buffered, converted into two 8-bit frame signals, and then transmitted in the original twisted pair data format. Return to the original receiving system.
3.2 1000BASE-T physical layer
The transmission medium of the 1000BASE-T physical layer is 4 pairs of unshielded twisted pair cables. The transmission rate of each pair of twisted pairs is 250.
Mbit/s; the functions implemented by the physical layer include:
(1) Interface with the MAC layer
Receive 8bit, 125M image data from the controller or restore the recovered data to the physical layer through the GMII interface
Upload to the main controller.
(2) The transmitting end scrambles the data, and the receiving end descrambles when the data of the transmitting end exhibits some periodic change, the signal frequency component is single, and is susceptible to crosstalk or interference. For example, the source end repeatedly transmits data 1010 and 1100, 4 pairs. The waveform signal change on the twisted pair line is shown in Figure 3. The signal in the figure uses the NRZ code. The principle is that when the signal "1" is encountered, the level is inverted, and when the signal is "0", the level is unchanged. It can be seen from the figure that the waveform of the entire "1" at the left end has the highest frequency and the frequency is determined. By scrambling the data, a fixed frequency signal will not be transmitted in a single clock cycle, and the signal energy will be distributed over a range of frequencies, effectively whitening the signal frequency components. This analog adds signal white noise transmission mode, so that the crosstalk signal generated between the twisted pairs is not related to the transmission data, and the receiving end can more easily distinguish the data signal from the noise signal.
(3) PAM5-4D level shifting
1000BASE-T distributes 8bit data on 4 pairs of twisted pairs and transmits them according to PAM5 signal. PAM5 is in advance
Five level standards (-2, -1, 0, 1, 2) are determined on the transmission line. Each level represents 2 bits of data information. When transmitting this level signal at a clock frequency of 125 M, the data rate is 250 Mbit/s. Among them, 5 levels are divided into two groups of (-1, 1) and (-2, 0, 2) signal elements, which ensure that the same subgroup minimum Euclidean distance [10] is maximized and enters the same state or leaves the same The Euclidean distance between different subgroups of the state is maximized. The second-level coding uses 4-dimensional 8-state trellis forward error correction Trellis [11] coding, and Viterbi [12] decoding at the receiving end, which increases the transmission error correction capability.
3.3 1000BASE-LX physical layer
The construction of the system fiber transport physical layer includes 8B/10B encoding [12], parallel-to-serial conversion, and level shifting of signals.
(1) 8B/10B coding is a kind of channel coding, which is a process of converting 8-bit data to be transmitted into 10-bit data according to a certain coding mode. 8B/10B encoding makes the number of consecutive "0" or "1" in the data stream no more than 5, which can effectively avoid data loss caused by clock drift of the receiving end; realize DC compensation and error detection function; and can transmit Specific control characters. The imbalance of the DC balance code is calculated by subtracting the number of "1"s from the number of "0"s in the codeword. The 8B/10B code divides the 8-bit data into 3 groups and 5 groups, which correspond to 4 bits and 6 bits out of 10 bits. The number of bits in the two groups after encoding is even, so the imbalance between the two groups. The degree is 0, ±2.
The 8B/10B code encodes each set of unbalanced values that are non-zero after encoding with two codewords, so that the coded value unbalance of the entire code is 0; and the last 6 bits of the previous code and the former code The sum of the 4-bit imbalances is also zero, thus achieving error detection and DC balance.
(2) parallel conversion
The optical signal is transmitted as a carrier, and the binary data 0 or 1 is represented by the light and dark of the light in a unit symbol period. So in number
According to the need to serialize the optical module before entering the optical module to meet the optical transmission needs.
The interface between the fiber physical layer chip and the MAC layer selected in this design is a 16-bit data bus. The FPGA host controller inputs 16 bits of data to be transmitted to the chip through a 125 Mbit/s clock. After the data channel is encoded by the dual 8B/10B encoder, the number of data bits becomes 20 bits. The input clock is multiplied by 20 times, and the data to be transmitted is serially output to the optical module as a differential signal after serial conversion. The total transmission rate is:
125 Mbit/s×20=2.5 Gbit/s;
Since the 8B/10B encoding efficiency is 80%, it is effectively transmitted.
The transmission rate is:
2.5 Gbit/s × 0.8 = 2 Gbit/s;
Matches the 1000BASE-T transmission rate.
(3) The differential level of the physical layer chip output is CML level, and the level standard that the optical module generally receives is LVPECL, string
The corresponding level shift is required before the line signal enters the optical module. Level matching, impedance matching and coupling matching of the input and output terminals are required during the conversion process. For the connection of LVPECL to CML, the AC coupling mode is selected in the design. 180Ω ground bias resistor is added to the two outputs of LVPECL, and 25 Ω resistors are respectively connected in the signal channel to make the LVPECL signal swing within the CML receiving range. For the connection of CML to LVPECL, the receiving end needs to pull up the 2.7kΩ resistor and pull down the 4.3kΩ resistor to make the CML level within the receiving range of LVPECL.
3.4 Master FPGA Design
The FPGA design structure is shown in Figure 4. Taking 1000BASE-T as the receiving end and 1000BASE-LX as the transmitting end as an example, the working process of the master FPGA is discussed.
The data signal sent to the FPGA by the 1000BASE-T physical layer is an 8-bit signal with 125 clocks of 125M. The data frame content includes: frame header, control data, image data, and frame tail; 1 bit of binary data is 1 character. The frame header contains 4 characters: 7C, D2, 15 and D8 respectively; control data 2 characters: CON1, CON2 contain the specific information of the current frame; each frame uses 256 columns of 24-bit RGB image data as the transmission content, therefore, the conversion There are 768 characters after 8 bits of data, and 6 characters at the end of the frame are "0", and each frame has a total of 780 characters. The MAC layer control module of 1000BASE-T is responsible for monitoring the data frame. When it receives the valid frame header signal, the control FIFO write control module turns on the corresponding write enable signal, and writes the effective image data into the corresponding FPGA chip. In the FIFO. At the same time, the FIFO read control module is controlled to read out the corresponding data already stored in the FIFO and send it to the MAC layer of 1000BASE-LX. The image data is stored in the FPGA using the "ping-pong" operation mode. In the design, four FIFOs (bit width is 8 bits and depth is 768) are instantiated, and each of the two groups is a group. When the two-port image frame data arrives, Two FIFOs (for example, FIFO_A, FIFO_B) perform 8-bit write operations, respectively; while data in FIFO_C and FIFO_D are read out and form a set of 16-bit data. When the next frame of image data arrives, FIFO_C and FIFO_D are written, and FIFO_A and FIFO_B are read. The read and write clocks are all 125Mbit/s, the dual port 8bit matches the single port 16bit, and there is a proper gap between each frame to ensure that the FIFO does not overflow. The MAC layer of 1000BASE-LX still needs to be “packaged” for the data read from the FIFO to ensure the validity of the transmission. The frame structure is the same as that of the twisted pair, and the unit character is changed from 8 bits to 16 bits. The first four characters of the frame are: 557C, 55D2, 5515 and 55D8; control signals [CON1_C, CON1_D], [CON2_C, CON2_D]
FIFO_C and FIFO_D are being read out) to form 2 characters respectively.
The image data in the FIFO is combined at the same position, containing 768 characters, 6 characters at the end of the frame, "0", and each frame is still 780 words.
Composition. The transmission of 1000BASE-LX is synchronized with the receiving process of 1000BASE-T. The data after “packaging” is sent to the physical layer of the optical fiber, and the optical fiber is transmitted to the remote end after electro-optical conversion, that is, the medium conversion of the twisted pair to the optical fiber is realized.
At the other end of the transmission system, the optical signal can be directly utilized or reconverted into a twisted pair signal according to the actual transmission medium requirement. When 1000BASE-LX reception and 1000BASE-T transmission, the data flow direction is opposite to the above process, and the design process the same.
4 Design verification
The data simulation of the 1000BASE-T receiving end is shown in the first two lines of Figure 5. In the figure, 7C, D2, 15, and D8 are frame headers, 00 and 34 are control data, and 34 is the current transmission of frame 52 (hexadecimal). 34), 00, 01... is experimental image data, incrementing by 256 (FF) for one cycle, 768 data characters are exactly 3 cycles, FE, FF is the data tail, 00 is the frame tail; 1000BASE-LX The transmission part of the simulation is shown in the last two lines of Figure 5. In the figure, 557C, 55D2, 5515, and 55D8 are frame headers, and 0000 and 3534 are control data, indicating adjacent 53 and 52 frames (hex 35, 34). , 0000, 0101...FEFE, FFFF are the image data just received and forwarded, and the end of the frame is 6 0000. It can be seen from the figure that two independent 1000BASE-T data frames successfully implement the single frame 1000BASE-LX. Forward.
The 1000BASE-T MAC layer FIFO read and write control samples are shown in Figure 6 (obtained using ALTERA's Signaltap). In the figure, P0_CLK and P0_rxdv and P0_rxdata are the receiving clock, receiving enable and 8-bit data signals of 1000BASE-T P0 port respectively. It can be seen that the data is valid starting at 7C, D2, .... P0_CON1 and P0_CON2 are 8-bit registers that enable separate storage of control signals. Each FIFO is reset before writing to prevent the previous read operation from reading the empty FIFO, causing data to remain and affecting this read operation. Fifo1_wen writes an enable signal for FIFO_A, aligned with the valid test pixel start data 00. The meaning of each signal in the P1 part is consistent with P0; since it is two independent data frames, the starting position of the timing corresponding to the receiving clock and enable may be different. In the figure, the P0 port and the P1 port are different by half a clock. Cycle; fifo3_4_ren is the FIFO_C, FIFO_D read enable signal, which is triggered by P0_rxdv and P1_rxdv to realize simultaneous reading of FIFO_C and FIFO_D. The read 16-bit data is fifo_data, which is directly sent to the 1000BASE-LX MAC layer for encapsulation into frames. And real-time forwarding is achieved.
5 Conclusion
The principle and specific implementation method of Gigabit Ethernet 1000BASE-T and 1000BASELX standards are introduced. Through the comparison of the physical layer, the medium conversion system is designed, so that the transmission mode of twisted pair and optical fiber can be effectively applied to the LED transmission system. Compared with the related Gigabit network media converter, the system performs MAC layer unpacking of the transmission frame and Re-encapsulation, the media conversion is deepened to the MAC layer, and the control instructions are separately cached, which is different from the simple physical layer data frame forwarding, which provides a design basis for the subsequent route design between the screen and the control board; the frame structure in the transmission is performed. Analysis, designed a data format compatible with the original transmission system, buffering each frame of data in the FPGA controller, increasing the stability of the transmission and matching the transmission rate. 1000BASET uses PAM5 level to make the twisted-pair single-channel transmission effective rate up to 1Gbit/s; 1000BASE-LX passes 8B/10B encoding, the actual transmission rate is 2.5Gbit/s, and the effective rate is 2Gbit/s, which realizes the dual-channel dual Matching of the strands. Test results show that the application of the media converter to the LED transmission system can improve the LED
The interconnection flexibility of the transmission system reduces the cost of the network in the case of ensuring the transmission distance. At the same time, the converter has practical reference significance for the long-distance transmission of the video source.
